Designed in advanced silicon geometry (TSMC 5nm node), the architecture has been built from the ground up to address high-performance computing problems in reliability, security and energy consumption to serve all performance-demanding market segments.
Founded in 2020, Ceremorphic leverages its own patented multi-thread processor technology ThreadArch combined with cutting-edge new technology developed by its own team of silicon, algorithm and software engineers to design an ultra-low-power training supercomputing chip.
“Having developed many innovations in multi-thread processing, algorithm driven VLSI, reliable performance circuits, low-energy interface circuits, quantum resistant security microarchitecture, and new device architectures beyond CMOS, Ceremorphic is well on its way to accomplish our goals,” explained Venkat Mattela, Founder and CEO of Ceremorphic. “The challenges this market faces with “reliable performance computing” cannot be solved with existing architectures, but rather needs a completely new architecture built specifically to provide reliability, security, energy efficiency, and scalability.”
The Hierarchical Learning Processor (HLP) that's been developed deploys the right processing system for optimal power performance operation. Key features of the QS 1 include the following:
- Custom Machine Learning Processor (MLP) running at 2GHz
- Custom FPU running at 2GHz
- Patented Multi-thread processing macro-architecture, ThreadArch based RISC –V processor for proxy processing (1GHz)
- Custom video engines for Metaverse Processing (1GHz) along with M55 v1 core from ARM
- Custom designed X16 PCIe 6. 0 / CXL 3.0 connectivity interface
- Open AI framework software support with optimized compiler and application libraries
- Soft error rate: (100,000)-1
The Ceremorphic architecture has been designed to scale across multiple compute intensive markets and applications, including AI training supercomputing, data centre processing, automotive, metaverse processing, robotics and life sciences.
