Patented technology, deep technical expertise & proven management

Ceremorphic was founded in April 2020 by industry veteran Dr. Venkat Mattela, Founder & CEO of Redpine Signals. Under his leadership, Redpine Signals delivered breakthrough innovations and industry first products leading to the development of an ultra-low power wireless solution which outperformed products from wireless industry giants by as much as 26 times in energy efficiency. Silicon Labs acquired Redpine Signals’ wireless assets for $308 million in March 2020.

Ceremorphic is designing an ultra-lower power supercomputing chip built in TSMC 5nm, leveraging its own patented technology and multi-thread processing architecture, ThreadArch® .

Our management team

Venkat Mattela, PhD

Founder and
Chief Executive Officer

Heonchul Park, PhD

Vice President, Processor Engineering

Kerman Katrak

Vice President, Human Resources

Mohammad Ahsan Raza

Director of Engineering, Logic and System Design

Srisubha Kalanadhabhatta, PhD

Director of Engineering, Reliability

Ajay Mantha

Director of Engineering, High Performance Analog

Govardhan Mattela

Director of Engineering, Algorithms and Software

Vaibhavi Desai

Director of Finance

Our board of directors

Venkat Mattela, PhD

Chairman (BoD)

Kalpana Atluri

Director

Mallik Reddy

Director

Our advisors

Jorge del Calvo

Partner at Pillsbury Winthrop Shaw Pittman, LLP

Rajiv Lal

Professor, Harvard Business School

Subhasish Mitra

Professor, Stanford University

Shan X Wang

Professor, Stanford University

Lizy Kurian John

Professor, University of Texas

Max Shulaker

Associate Professor, MIT

Venkat Mattela, PhD

Founder and Chief Executive Officer

Venkat has over three decades of engineering and management experience in developing differentiated products and building successful businesses. Prior to founding Ceremorphic, he founded Redpine Signals, Inc., a wireless technology company that he sold to Silicon Labs, Inc. for $308M. Previously, Venkat held roles as Director of Engineering, Network Media Processors for Analog devices, and Director of Engineering, TriCore – MCU DSP for Infineon Technologies. He started his career at Tata Institute of Fundamental Research, India in January 1983. Venkat holds a PhD in Electrical Engineering from Indian Institute of Technology and is a graduate of Harvard Business School. Venkat has over 100 US and international patents.

Venkat Mattela, PhD

Founder and Chief Executive Officer

Venkat has over three decades of engineering and management experience in developing differentiated products and building successful businesses. Prior to founding Ceremorphic, he founded Redpine Signals, Inc., a wireless technology company that he sold to Silicon Labs, Inc. for $308M. Previously, Venkat held roles as Director of Engineering, Network Media Processors for Analog devices, and Director of Engineering, TriCore – MCU DSP for Infineon Technologies. He started his career at Tata Institute of Fundamental Research, India in January 1983. Venkat holds a PhD in Electrical Engineering from Indian Institute of Technology and is a graduate of Harvard Business School. Venkat has over 100 US and international patents.

Heonchul Park, PhD

Vice President, Processor Engineering

Heonchul leads the architecture and design of all processing systems at CeremorphicHe has over three decades of experience in engineering and technical management of processor designs. Heonchul  began his career at Samsung after he received his PhD from the University of Southern California in Computer Engineering. He has held key roles working on semiconductor designs at Samsung, Siemens, Infineon, and Redpine Signals.  Heonchul led the engineering at Redpine Signals as Vice President. He is the inventor of Ceremorphic’s patented multi-thread processor architecture, ThreadArch®  He has published various articles including IEEE Transaction papers and holds more than 20 US patents. 

Heonchul Park, PhD

Vice President, Processor Engineering

Heonchul leads the architecture and design of all processing systems at CeremorphicHe has over three decades of experience in engineering and technical management of processor designs. Heonchul  began his career at Samsung after he received his PhD from the University of Southern California in Computer Engineering. He has held key roles working on semiconductor designs at Samsung, Siemens, Infineon, and Redpine Signals.  Heonchul led the engineering at Redpine Signals as Vice President. He is the inventor of Ceremorphic’s patented multi-thread processor architecture, ThreadArch®  He has published various articles including IEEE Transaction papers and holds more than 20 US patents. 

Kerman Katrak

Vice President, Human Resources

Kerman is a human resource professional with more than two decades of experience in various industries and regions. Previously, Kerman held head HR/senior management positions at Nomura, Lehman Brothers, Union National Bank, ERCO, and Vanenburg & Godrej. He has extensive knowledge and experience of recruitment and selection, manpower planning & analysis, performance management, compensation & benefits, HR policies, training & development, business process planning, employee/industrial relations and labor laws. Kerman has a master’s degree in Personnel Management & Industrial Relations from the Tata Institute of Social Sciences, Mumbai. 

Kerman Katrak

Vice President, Human Resources

Kerman is a human resource professional with more than two decades of experience in various industries and regions. Previously, Kerman held head HR/senior management positions at Nomura, Lehman Brothers, Union National Bank, ERCO, and Vanenburg & Godrej. He has extensive knowledge and experience of recruitment and selection, manpower planning & analysis, performance management, compensation & benefits, HR policies, training & development, business process planning, employee/industrial relations and labor laws. Kerman has a master’s degree in Personnel Management & Industrial Relations from the Tata Institute of Social Sciences, Mumbai. 

Mohammad Ahsan Raza

Director of Engineering, Logic and System Design

Ahsan has over 20 years of experience in the field of hardware and software development. Ahsan leads the logic and systems design team in Ceremorphic developing high performance and low power logic for connectivity processors for next-generation AI and ML systems. He also leads the FPGA emulation of the system-on-chip (SoC) platform within Ceremorphic. Previously, Ahsan was Director of Engineering at Reniac and Senior Engineering Manager at Xilinx. Before that, he was a Senior Design Engineer in Adaptec.

Ahsan holds a Bachelor of Technology degree from Nagpur University in Electronics Engineering and a Master of Science (Research) in Electronics and Communication Engineering from International Institute of Information Technology Hyderabad.

Mohammad Ahsan Raza

Director of Engineering, Logic and System Design

Ahsan has over 20 years of experience in the field of hardware and software development. Ahsan leads the logic and systems design team in Ceremorphic developing high performance and low power logic for connectivity processors for next-generation AI and ML systems. He also leads the FPGA emulation of the system-on-chip (SoC) platform within Ceremorphic. Previously, Ahsan was Director of Engineering at Reniac and Senior Engineering Manager at Xilinx. Before that, he was a Senior Design Engineer in Adaptec.

Ahsan holds a Bachelor of Technology degree from Nagpur University in Electronics Engineering and a Master of Science (Research) in Electronics and Communication Engineering from International Institute of Information Technology Hyderabad.

Srisubha Kalanadhabhatta, PhD

Director of Engineering, Reliability

Srisubha has over 18 years of experience in VLSI Engineering and technical management. She is responsible for architecture and designing reliable systems and test systems for Ceremorphic system-on-chips (SoCs). Previously, Srisubha worked at Redpine Signals for 15 years and was responsible for test and clock architectures, silicon validation and qualification. Srisubha holds a Doctoral degree in Hardware Security from Indian Institute of Technology, Hyderabad and a master’s degree in VLSI from National Institute of Technology, Trichy.

Srisubha Kalanadhabhatta, PhD

Director of Engineering, Reliability

Srisubha has over 18 years of experience in VLSI Engineering and technical management. She is responsible for architecture and designing reliable systems and test systems for Ceremorphic system-on-chips (SoCs). Previously, Srisubha worked at Redpine Signals for 15 years and was responsible for test and clock architectures, silicon validation and qualification. Srisubha holds a Doctoral degree in Hardware Security from Indian Institute of Technology, Hyderabad and a master’s degree in VLSI from National Institute of Technology, Trichy.

Ajay Mantha

Director of Engineering, High Performance Analog

Ajay has over 15 years of experience in engineering and technical management. Ajay is responsible for all the high-speed analog, mixed signal and custom memory development at Ceremorphic. Prior to joining Ceremorphic, he was the India Centre Head and Director of Engineering at Keyssa Inc. Before that, he served as Director of Engineering at Redpine signals Inc. for 12 years and was a founding member of the RFIC team that was later acquired by Silicon Labs.  He holds an MSEE degree from Stanford University and a B. Tech degree from IIT Guwahati. Ajay holds 4+ patents related to low power wireless designs. 

Ajay Mantha

Director of Engineering, High Performance Analog

Ajay has over 15 years of experience in engineering and technical management. Ajay is responsible for all the high-speed analog, mixed signal and custom memory development at Ceremorphic. Prior to joining Ceremorphic, he was the India Centre Head and Director of Engineering at Keyssa Inc. Before that, he served as Director of Engineering at Redpine signals Inc. for 12 years and was a founding member of the RFIC team that was later acquired by Silicon Labs.  He holds an MSEE degree from Stanford University and a B. Tech degree from IIT Guwahati. Ajay holds 4+ patents related to low power wireless designs. 

Govardhan Mattela,

Director of Engineering, Algorithms and Software

Govardhan has more than 13 years of engineering and technical management experience. At Ceremorphic, he is leading the algorithms and system engineering teams and develops new algorithms in machine learning, compiler technology, computer networks and security software protocols. Previously, Govardhan worked at Redpine Signals where he developed 802.11p vehicular communication protocol stacks, and he also served as technical lead at Cisco ODC Group of HCL technologies. He holds a master’s degree in Data Science Algorithms (M. Tech) from Indian Institute of Technology, Hyderabad. He has 2 granted patents and is the author of 8 publications.

Govardhan Mattela,

Director of Engineering, Algorithms and Software

Govardhan has more than 13 years of engineering and technical management experience. At Ceremorphic, he is leading the algorithms and system engineering teams and develops new algorithms in machine learning, compiler technology, computer networks and security software protocols. Previously, Govardhan worked at Redpine Signals where he developed 802.11p vehicular communication protocol stacks, and he also served as technical lead at Cisco ODC Group of HCL technologies. He holds a master’s degree in Data Science Algorithms (M. Tech) from Indian Institute of Technology, Hyderabad. He has 2 granted patents and is the author of 8 publications.

Vaibhavi Desai

Director of Finance

Vaibhavi is a finance and operations professional with over 18 years of experience working in the banking and technology industries. At Ceremorphic, she manages finance and compliance functions for US and India entities. She previously worked with CipherCloud, a security technology company, and Redpine Signals, both in Silicon Valley. Vaibhavi has a strong background in managing the financial due-diligence process in M&A transactions. Her credentials include CMA (US) and CFA-ICFAI (India).

Vaibhavi Desai

Director of Finance

Vaibhavi is a finance and operations professional with over 18 years of experience working in the banking and technology industries. At Ceremorphic, she manages finance and compliance functions for US and India entities. She previously worked with CipherCloud, a security technology company, and Redpine Signals, both in Silicon Valley. Vaibhavi has a strong background in managing the financial due-diligence process in M&A transactions. Her credentials include CMA (US) and CFA-ICFAI (India).

Venkat Mattela, PhD

Chairman (BoD)

Venkat has over three decades of engineering and management experience in developing differentiated products and building successful businesses. Prior to founding Ceremorphic, he founded Redpine Signals, Inc., a wireless technology company that he sold to Silicon Labs, Inc. for $308M. Previously, Venkat held roles as Director of Engineering, Network Media Processors for Analog devices, and Director of Engineering, TriCore – MCU DSP for Infineon Technologies. He started his career at Tata Institute of Fundamental Research, India in January 1983. Venkat holds a PhD in Electrical Engineering from Indian Institute of Technology and is a graduate of Harvard Business School. Venkat has over 100 US and international patents.

Venkat Mattela, PhD

Chairman (BoD)

Venkat has over three decades of engineering and management experience in developing differentiated products and building successful businesses. Prior to founding Ceremorphic, he founded Redpine Signals, Inc., a wireless technology company that he sold to Silicon Labs, Inc. for $308M. Previously, Venkat held roles as Director of Engineering, Network Media Processors for Analog devices, and Director of Engineering, TriCore – MCU DSP for Infineon Technologies. He started his career at Tata Institute of Fundamental Research, India in January 1983. Venkat holds a PhD in Electrical Engineering from Indian Institute of Technology and is a graduate of Harvard Business School. Venkat has over 100 US and international patents.

Kalpana Atluri

Director

Kalpana has over 30 years of experience in the semiconductor industry. Prior to founding Redpine Signals, she founded Elite Design Systems, a provider of ASIC design consulting services. At Ceremorphic, she manages the global HR and corporate operations in the US and India. She has held various engineering positions at Synopsys Inc., Computer Vision Laboratories Ltd., CMC Ltd., and Integrated Data Systems. She holds a master’s degree in Electrical Engineering from JNTU, India.

Kalpana Atluri

Director

Kalpana has over 30 years of experience in the semiconductor industry. Prior to founding Redpine Signals, she founded Elite Design Systems, a provider of ASIC design consulting services. At Ceremorphic, she manages the global HR and corporate operations in the US and India. She has held various engineering positions at Synopsys Inc., Computer Vision Laboratories Ltd., CMC Ltd., and Integrated Data Systems. She holds a master’s degree in Electrical Engineering from JNTU, India.

Mallik Reddy

Director

Mallik is a seasoned entrepreneur and executive with over 30 years of management and engineering experience. He was previously with Redpine Signals and he also founded Netcube Systems, a leading provider of technology consulting services for a broad spectrum of Fortune 500 and Fortune 1000 companies. Prior to that, he held key management and engineering positions at Pelican, Softec, Sybase, E-trade SUN, Oracle, TIBCO, and AC Nielsen. Mallik holds an MS in Computer Science from the University of Florida.​

Mallik Reddy

Director

Mallik is a seasoned entrepreneur and executive with over 30 years of management and engineering experience. He was previously with Redpine Signals and he also founded Netcube Systems, a leading provider of technology consulting services for a broad spectrum of Fortune 500 and Fortune 1000 companies. Prior to that, he held key management and engineering positions at Pelican, Softec, Sybase, E-trade SUN, Oracle, TIBCO, and AC Nielsen. Mallik holds an MS in Computer Science from the University of Florida.​

Jorge del Calvo 

Partner at Pillsbury Winthrop Shaw Pittman, LLP

Jorge del Calvo is a partner with Pillsbury, Winthrop Shaw Pittman, a global law firm and over the past 39 years has represented public and private technology companies in mergers and acquisitions, public offerings, private placements and joint ventures, investment banks in equity, debt and other transactions, and venture and private equity funds in their formation and investments. Jorge’s clients range in size from unfunded start-ups to Fortune 500 companies. He is particularly experienced with the business and legal issues implicated by rapid growth and disruptive technologies. Twenty of the companies Jorge has represented achieved valuations in excess of $1 billion. Ten of these twenty companies were represented by Jorge since their incorporation. Jorge was chosen out of approximately 186,000 California lawyers as one of the “Top 100 Lawyers” in the state from 2014-2017 by the Daily Journal (California’s leading legal newspaper). He was ranked by Chambers USA among the top lawyers in California for Capital Markets: Debt and Equity from 2014-2021 and on the national level for Investment Funds:  Law and Venture Capital Law from 2006-2022. Jorge is currently serving on the Board of Directors of Ouster (Oust), a publicly-traded company and has previously served on the Board of a number of other publicly-traded companies. He is a graduate of Harvard Law School and Stanford University (Bachelor of Arts).

Jorge del Calvo 

Partner at Pillsbury Winthrop Shaw Pittman, LLP

Jorge del Calvo is a partner with Pillsbury, Winthrop Shaw Pittman, a global law firm and over the past 39 years has represented public and private technology companies in mergers and acquisitions, public offerings, private placements and joint ventures, investment banks in equity, debt and other transactions, and venture and private equity funds in their formation and investments. Jorge’s clients range in size from unfunded start-ups to Fortune 500 companies. He is particularly experienced with the business and legal issues implicated by rapid growth and disruptive technologies. Twenty of the companies Jorge has represented achieved valuations in excess of $1 billion. Ten of these twenty companies were represented by Jorge since their incorporation. Jorge was chosen out of approximately 186,000 California lawyers as one of the “Top 100 Lawyers” in the state from 2014-2017 by the Daily Journal (California’s leading legal newspaper). He was ranked by Chambers USA among the top lawyers in California for Capital Markets: Debt and Equity from 2014-2021 and on the national level for Investment Funds:  Law and Venture Capital Law from 2006-2022. Jorge is currently serving on the Board of Directors of Ouster (Oust), a publicly-traded company and has previously served on the Board of a number of other publicly-traded companies. He is a graduate of Harvard Law School and Stanford University (Bachelor of Arts).

Rajiv Lal

STANLEY ROTH, SR. PROFESSOR OF RETAILING CO-UNIT HEAD, MARKETING

Rajiv Lal is the Stanley Roth, Sr. Professor of Retailing at Harvard Business School. He is currently teaching an elective MBA course on the Business of Smart Connected Products/IOT. He has been responsible for the retailing curriculum and has served as the course head for Marketing, required study in the first year of the MBA program. Professor Lal also teaches in several Executive Education programs, has previously served as the Faculty Chair for the General Management Program, and the program on Building and Leading a Customer Centric Organization.

Lal was a Professor at the Graduate School of Business at Stanford University beginning in 1982. He was the Thomas Henry Carroll Ford Foundation Visiting Professor at Harvard Business School from 1997-98. He was the Visiting Professor of Marketing at INSEAD, France in 1986, 1988, 1992, and 1993. He did his undergraduate work in Mechanical Engineering at the Indian Institute of Technology at Kanpur, India and received his Ph.D. in Industrial Administration from Carnegie-Mellon University.

Lal’s current research concerns the opportunities and challenges in building a Business around Smart Connected products/IOT. His book “Retail Revolution: Will Your Store Survive” is based on many years of extensive research in the field of Retailing focusing on the viability of brick-and-mortar stores as they face the onslaught of on-line competition. In addition, he has studied how to build and sustain customer-centric retail organizations. His past work has explored successful retail strategies for global expansion. He has written extensively on the impact of using the Internet as a channel of distribution on a retailer’s pricing, merchandising, and branding strategy. His earlier work in retailing studies the impact of competition between different retail formats, such as EDLP and Hi-Lo grocers. He has also studied the consequences of grocery retailers’ increasing use of store brands on store loyalty and its implications for packaged goods manufacturers.

Lal’s earlier research focused on pricing, trade promotions, and salesforce compensation plans. The work on salesforce compensation plans originated with his dissertation research, which won the award for the best paper published in Marketing Science and Management Science in 1985. A subsequent article, also developed from his thesis, received an honorable mention for the same award in 1986. He has also studied compensation plans used by German salesforces.

His work in the area of pricing and promotions has been equally well recognized. Two of his articles were among the finalists for the John D. C. Little award for the best paper published in Management Science and Marketing Science in 1990. One of these articles, co-authored with Jagmohan Raju and V. Srinivasan on the impact of brand loyalty on price promotions, has been awarded the Frank Bass award for the best dissertation paper.

Lal’s recent work includes Retail Revolution: Will Your Brick-and-Mortar Store Survive?, “Retail Doesn’t Cross Borders: Here’s Why and What to do About it” in Harvard Business Review, “Retailing Revolution: Category Killers on the Brink” in HBS Working Knowledge, and Marketing Management: Text and Cases. He has published more than twenty-five articles in academic journals and more than 80 cases and other teaching materials. He has applied his academic frameworks and industry knowledge in much of his research and many of his consulting projects.

Lal has worked on a variety of such projects with a wide range of companies, including Citigroup, Citizens Bank, American Family Insurance, Standard Life Plc, Omnitel Italia, Credit Suisse, Stop & Shop, Ito-Yokado, Best Buy, Stride Rite Corporation, Oliver Wyman and Company, Fleming Companies, Nordstrom, Microsoft, Kellogg, Sara Lee D/E, Novartis Pharmaceuticals, Callaway Golf Company, Staples, and other well-known companies on strategy development and execution.

Lal serves as a member of the Board for Leader Bank and Global Cures. In addition to these board positions, Lal has served as an Area Editor for Marketing Science and Co-editor of Quantitative Marketing and Economics.

Rajiv Lal

STANLEY ROTH, SR. PROFESSOR OF RETAILING CO-UNIT HEAD, MARKETING

Rajiv Lal is the Stanley Roth, Sr. Professor of Retailing at Harvard Business School. He is currently teaching an elective MBA course on the Business of Smart Connected Products/IOT. He has been responsible for the retailing curriculum and has served as the course head for Marketing, required study in the first year of the MBA program. Professor Lal also teaches in several Executive Education programs, has previously served as the Faculty Chair for the General Management Program, and the program on Building and Leading a Customer Centric Organization.

Lal was a Professor at the Graduate School of Business at Stanford University beginning in 1982. He was the Thomas Henry Carroll Ford Foundation Visiting Professor at Harvard Business School from 1997-98. He was the Visiting Professor of Marketing at INSEAD, France in 1986, 1988, 1992, and 1993. He did his undergraduate work in Mechanical Engineering at the Indian Institute of Technology at Kanpur, India and received his Ph.D. in Industrial Administration from Carnegie-Mellon University.

Lal’s current research concerns the opportunities and challenges in building a Business around Smart Connected products/IOT. His book “Retail Revolution: Will Your Store Survive” is based on many years of extensive research in the field of Retailing focusing on the viability of brick-and-mortar stores as they face the onslaught of on-line competition. In addition, he has studied how to build and sustain customer-centric retail organizations. His past work has explored successful retail strategies for global expansion. He has written extensively on the impact of using the Internet as a channel of distribution on a retailer’s pricing, merchandising, and branding strategy. His earlier work in retailing studies the impact of competition between different retail formats, such as EDLP and Hi-Lo grocers. He has also studied the consequences of grocery retailers’ increasing use of store brands on store loyalty and its implications for packaged goods manufacturers.

Lal’s earlier research focused on pricing, trade promotions, and salesforce compensation plans. The work on salesforce compensation plans originated with his dissertation research, which won the award for the best paper published in Marketing Science and Management Science in 1985. A subsequent article, also developed from his thesis, received an honorable mention for the same award in 1986. He has also studied compensation plans used by German salesforces.

His work in the area of pricing and promotions has been equally well recognized. Two of his articles were among the finalists for the John D. C. Little award for the best paper published in Management Science and Marketing Science in 1990. One of these articles, co-authored with Jagmohan Raju and V. Srinivasan on the impact of brand loyalty on price promotions, has been awarded the Frank Bass award for the best dissertation paper.

Lal’s recent work includes Retail Revolution: Will Your Brick-and-Mortar Store Survive?, “Retail Doesn’t Cross Borders: Here’s Why and What to do About it” in Harvard Business Review, “Retailing Revolution: Category Killers on the Brink” in HBS Working Knowledge, and Marketing Management: Text and Cases. He has published more than twenty-five articles in academic journals and more than 80 cases and other teaching materials. He has applied his academic frameworks and industry knowledge in much of his research and many of his consulting projects.

Lal has worked on a variety of such projects with a wide range of companies, including Citigroup, Citizens Bank, American Family Insurance, Standard Life Plc, Omnitel Italia, Credit Suisse, Stop & Shop, Ito-Yokado, Best Buy, Stride Rite Corporation, Oliver Wyman and Company, Fleming Companies, Nordstrom, Microsoft, Kellogg, Sara Lee D/E, Novartis Pharmaceuticals, Callaway Golf Company, Staples, and other well-known companies on strategy development and execution.

Lal serves as a member of the Board for Leader Bank and Global Cures. In addition to these board positions, Lal has served as an Area Editor for Marketing Science and Co-editor of Quantitative Marketing and Economics.

Subhasish Mitra

Professor, Department of Electrical Engineering and Department of Computer Science, Stanford University

Subhasish is Professor of Electrical Engineering and of Computer Science at Stanford University. He directs the Stanford Robust Systems Group, leads the Computation Focus Area of the Stanford SystemX Alliance, and is a member of the Wu Tsai Neurosciences Institute. His research ranges across Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences. Results from his research group have influenced almost every contemporary electronic system, and have inspired significant government and research initiatives in multiple countries. He has held several international academic appointments — the Carnot Chair of Excellence in NanoSystems at CEA-LETI in France, Invited Professor at EPFL in Switzerland, and Visiting Professor at the University of Tokyo in Japan. Prof. Mitra also has consulted for major technology companies including Cisco, Google, Intel, Samsung, and Xilinx.

In the field of Robust Computing, he has created many key approaches for circuit failure prediction, on-line diagnostics, QED system validation, soft error resilience, and X-Compact test compression. Their adoption by industry is growing rapidly, in markets ranging from cloud computing to automotive systems. His X-Compact approach has proven essential for cost-effective manufacturing and high-quality testing of almost all 21st century systems, enabling billions of dollars in cost savings.

With his students and collaborators, he demonstrated the first carbon nanotube computer. They also demonstrated the first 3D NanoSystem with computation immersed in data storage. These received wide recognition: cover of NATURE, Research Highlight to the US Congress by the NSF, and highlight as “important scientific breakthrough” by global news organizations.

Prof. Mitra’s honors include the Newton Technical Impact Award in EDA (test-of-time honor by ACM SIGDA and IEEE CEDA), the University Researcher Award (by the Semiconductor Industry Association and Semiconductor Research Corporation to recognize lifetime research contributions), the Intel Achievement Award (Intel’s highest honor), and the US Presidential Early Career Award. He and his students have published over 10 award-winning papers across 5 topic areas (technology, circuits, EDA, test, verification) at major venues including the Design Automation Conference, International Solid-State Circuits Conference, International Test Conference, Symposium on VLSI Technology, and Formal Methods in Computer-Aided Design. Stanford undergraduates have honored him several times “for being important to them.” He is an ACM Fellow and an IEEE Fellow.

Subhasish Mitra

Professor, Department of Electrical Engineering and Department of Computer Science, Stanford University

Subhasish is Professor of Electrical Engineering and of Computer Science at Stanford University. He directs the Stanford Robust Systems Group, leads the Computation Focus Area of the Stanford SystemX Alliance, and is a member of the Wu Tsai Neurosciences Institute. His research ranges across Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences. Results from his research group have influenced almost every contemporary electronic system, and have inspired significant government and research initiatives in multiple countries. He has held several international academic appointments — the Carnot Chair of Excellence in NanoSystems at CEA-LETI in France, Invited Professor at EPFL in Switzerland, and Visiting Professor at the University of Tokyo in Japan. Prof. Mitra also has consulted for major technology companies including Cisco, Google, Intel, Samsung, and Xilinx.

In the field of Robust Computing, he has created many key approaches for circuit failure prediction, on-line diagnostics, QED system validation, soft error resilience, and X-Compact test compression. Their adoption by industry is growing rapidly, in markets ranging from cloud computing to automotive systems. His X-Compact approach has proven essential for cost-effective manufacturing and high-quality testing of almost all 21st century systems, enabling billions of dollars in cost savings.

With his students and collaborators, he demonstrated the first carbon nanotube computer. They also demonstrated the first 3D NanoSystem with computation immersed in data storage. These received wide recognition: cover of NATURE, Research Highlight to the US Congress by the NSF, and highlight as “important scientific breakthrough” by global news organizations.

Prof. Mitra’s honors include the Newton Technical Impact Award in EDA (test-of-time honor by ACM SIGDA and IEEE CEDA), the University Researcher Award (by the Semiconductor Industry Association and Semiconductor Research Corporation to recognize lifetime research contributions), the Intel Achievement Award (Intel’s highest honor), and the US Presidential Early Career Award. He and his students have published over 10 award-winning papers across 5 topic areas (technology, circuits, EDA, test, verification) at major venues including the Design Automation Conference, International Solid-State Circuits Conference, International Test Conference, Symposium on VLSI Technology, and Formal Methods in Computer-Aided Design. Stanford undergraduates have honored him several times “for being important to them.” He is an ACM Fellow and an IEEE Fellow.

Shan X Wang

LELAND T. EDWARDS PROFESSOR IN THE SCHOOL OF ENGINEERING AND PROFESSOR OF ELECTRICAL ENGINEERING AND, BY COURTESY, OF RADIOLOGY (MOLECULAR IMAGING PROGRAM AT STANFORD)

Prof. Wang directs the Center for Magnetic Nanotechnology and is a leading expert in biosensors, information storage and spintronics. His research and inventions span across a variety of areas including magnetic biochips, in vitro diagnostics, cancer biomarkers, magnetic nanoparticles, magnetic sensors, magnetoresistive random access memory, and magnetic integrated inductors. He has authored over 300 publications and holds 65 issued or pending patents in these and interdisciplinary areas. He was named an inaugural Fred Terman Fellow and was elected a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) and a Fellow of American Physical Society (APS) for his seminal contributions to magnetic materials and nanosensors. His team won the Grand Challenge Exploration Award from Gates Foundation (2010), the XCHALLENGE Distinguished Award (2014), and the Bold Epic Innovator Award from the XPRIZE Foundation (2017).

Dr. Wang cofounded three high-tech startups in Silicon Valley, including MagArray, Inc. and Flux Biosciences, Inc. In 2018, MagArray launched a first of its kind lung cancer early diagnostic assay based on protein cancer biomarkers and support vector machine (SVM). In 2019, Flux Biosciences launched a human trial to offer at-home testing of fertility based on hormones and magneto-nanosensors. Through his participation in the Center for Cancer Nanotechnology Excellence (as co-PI of the CCNE) and the Joint University Microelectronics Program (JUMP), he is actively engaged in the transformative research of healthcare and is developing emerging memories for energy efficient computing. 

Shan X Wang

LELAND T. EDWARDS PROFESSOR IN THE SCHOOL OF ENGINEERING AND PROFESSOR OF ELECTRICAL ENGINEERING AND, BY COURTESY, OF RADIOLOGY (MOLECULAR IMAGING PROGRAM AT STANFORD)

Prof. Wang directs the Center for Magnetic Nanotechnology and is a leading expert in biosensors, information storage and spintronics. His research and inventions span across a variety of areas including magnetic biochips, in vitro diagnostics, cancer biomarkers, magnetic nanoparticles, magnetic sensors, magnetoresistive random access memory, and magnetic integrated inductors. He has authored over 300 publications and holds 65 issued or pending patents in these and interdisciplinary areas. He was named an inaugural Fred Terman Fellow and was elected a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) and a Fellow of American Physical Society (APS) for his seminal contributions to magnetic materials and nanosensors. His team won the Grand Challenge Exploration Award from Gates Foundation (2010), the XCHALLENGE Distinguished Award (2014), and the Bold Epic Innovator Award from the XPRIZE Foundation (2017).

Dr. Wang cofounded three high-tech startups in Silicon Valley, including MagArray, Inc. and Flux Biosciences, Inc. In 2018, MagArray launched a first of its kind lung cancer early diagnostic assay based on protein cancer biomarkers and support vector machine (SVM). In 2019, Flux Biosciences launched a human trial to offer at-home testing of fertility based on hormones and magneto-nanosensors. Through his participation in the Center for Cancer Nanotechnology Excellence (as co-PI of the CCNE) and the Joint University Microelectronics Program (JUMP), he is actively engaged in the transformative research of healthcare and is developing emerging memories for energy efficient computing.

Lizy Kurian John

Cullen Trust for Higher Education Endowed Professor, Department of Electrical and Computer Engineering

Dr. Lizy Kurian John holds the Cullen Trust for Higher Education Endowed Professorship in Engineering #3 in the Department of Electrical & Computer Engineering at The University of Texas at Austin.

She received her Ph.D. in computer engineering from The Pennsylvania State University in 1993. She joined The University of Texas Austin faculty in 1996. Her research is in the areas of computer architecture, multicore processors, memory systems, performance evaluation and benchmarking, workload characterization, and reconfigurable computing.

Professor John’s research has been supported by the National Science Foundation, Semiconductor Research Consortium (SRC), DARPA, Lockheed Martin, AMD, Oracle, Huawei, IBM, Intel, Motorola, Freescale, Dell, Samsung, Texas Instruments, etc.. She is recipient of NSF CAREER award (1996), UT Austin Engineering Foundation Faculty Award (2001), Halliburton, Brown and Root Engineering Foundation Young Faculty Award (1999), University of Texas Alumni Association Teaching Award (2004), The Pennsylvania State University Outstanding Engineering Alumnus (2011) etc.

Professor John holds 15 U. S. patents and has published 16 book chapters, approximately 300 journal and conference and workshop papers. She has coauthored books on Digital Systems Design using VHDL (Cengage Publishers 2007, 2017), Digital Systems Design using Verilog (Cengage Publishers, 2014) and has edited a book on Computer Performance Evaluation and Benchmarking (CRC Press). She has also edited three books on workload characterization.

Professor John is the Editor-in-Chief (EIC) of IEEE MICRO and has served in the editorial boards of IEEE Transactions on Computers, ACM Transactions on Architecture and Code Optimizations (TACO), IEEE Computer Architecture Letters, IEEE Transactions on Sustainable Computing, and IEEE Transactions on VLSI. She is a member of IEEE, IEEE Computer Society, ACM, and ACM SIGARCH.

John was named a Fellow of IEEE in 2009, a Fellow of the National Academy of Inventors in 2020, and a Fellow of the Association for Computing Machinery (Class of 2020).

Lizy Kurian John

Cullen Trust for Higher Education Endowed Professor, Department of Electrical and Computer Engineering

Dr. Lizy Kurian John holds the Cullen Trust for Higher Education Endowed Professorship in Engineering #3 in the Department of Electrical & Computer Engineering at The University of Texas at Austin.

She received her Ph.D. in computer engineering from The Pennsylvania State University in 1993. She joined The University of Texas Austin faculty in 1996. Her research is in the areas of computer architecture, multicore processors, memory systems, performance evaluation and benchmarking, workload characterization, and reconfigurable computing.

Professor John’s research has been supported by the National Science Foundation, Semiconductor Research Consortium (SRC), DARPA, Lockheed Martin, AMD, Oracle, Huawei, IBM, Intel, Motorola, Freescale, Dell, Samsung, Texas Instruments, etc.. She is recipient of NSF CAREER award (1996), UT Austin Engineering Foundation Faculty Award (2001), Halliburton, Brown and Root Engineering Foundation Young Faculty Award (1999), University of Texas Alumni Association Teaching Award (2004), The Pennsylvania State University Outstanding Engineering Alumnus (2011) etc.

Professor John holds 15 U. S. patents and has published 16 book chapters, approximately 300 journal and conference and workshop papers. She has coauthored books on Digital Systems Design using VHDL (Cengage Publishers 2007, 2017), Digital Systems Design using Verilog (Cengage Publishers, 2014) and has edited a book on Computer Performance Evaluation and Benchmarking (CRC Press). She has also edited three books on workload characterization.

Professor John is the Editor-in-Chief (EIC) of IEEE MICRO and has served in the editorial boards of IEEE Transactions on Computers, ACM Transactions on Architecture and Code Optimizations (TACO), IEEE Computer Architecture Letters, IEEE Transactions on Sustainable Computing, and IEEE Transactions on VLSI. She is a member of IEEE, IEEE Computer Society, ACM, and ACM SIGARCH.

John was named a Fellow of IEEE in 2009, a Fellow of the National Academy of Inventors in 2020, and a Fellow of the Association for Computing Machinery (Class of 2020).

Max Shulaker

Associate Professor at MIT, Electrical Engineering & Computer Science

Professor Max Shulaker joined the EECS department at MIT as an assistant professor in July 2016. He received his B.S., M.S., and Ph.D. from Stanford University in Electrical Engineering. During his Ph.D., his research on carbon nanotube-based transistors and circuits resulted in the first digital systems built entirely using carbon nanotube FETs (including the first carbon nanotube microprocessor), the first monolithic three-dimensional integrated circuits combining arbitrary vertical stacking of logic and memory, and the highest performance and highly-scaled carbon nanotube transistors to-date.

At MIT, Max is launching an experimental research program aimed at realizing his vision for the next-generation of electronic systems based on transformation nanosystems: leveraging the unique properties of emerging nanotechnologies and nanodevices to create new systems and architectures with enhanced functionality and improved performance. About this, he states: “While investigating new devices or new architectures separately can be beneficial, combining the “right” devices, with the “right” architectures, in the “right” way, results in performance (e.g., speed, energy efficiency) gains which far exceed the sum of their individual benefits, while simultaneously providing a rich set of enhanced functionality for applications that otherwise may not be feasible using traditional technologies.”

Max aims to drive nanosystems to both improve computing at the heart of information technology through new approaches (e.g., new system architectures directly enabled by new nanotechnologies). He plans to leverage the richness of new nanomaterials, new computing and memory technologies, and heterogeneous integration to enable new applications beyond the scope of traditional computing. His ultimate goal is to drive nanosystems from concept to reality, resulting in hardware demonstrations of what future electronic systems might look like: from 3D chips with layers of sensing, memory, and logic densely integrated for on-chip ultra-high bandwidth sensing and processing, to computation finely-immersed in biological systems for disease monitoring and nano-implants.

Max Shulaker

Associate Professor at MIT, Electrical Engineering & Computer Science

Professor Max Shulaker joined the EECS department at MIT as an assistant professor in July 2016. He received his B.S., M.S., and Ph.D. from Stanford University in Electrical Engineering. During his Ph.D., his research on carbon nanotube-based transistors and circuits resulted in the first digital systems built entirely using carbon nanotube FETs (including the first carbon nanotube microprocessor), the first monolithic three-dimensional integrated circuits combining arbitrary vertical stacking of logic and memory, and the highest performance and highly-scaled carbon nanotube transistors to-date.

At MIT, Max is launching an experimental research program aimed at realizing his vision for the next-generation of electronic systems based on transformation nanosystems: leveraging the unique properties of emerging nanotechnologies and nanodevices to create new systems and architectures with enhanced functionality and improved performance. About this, he states: “While investigating new devices or new architectures separately can be beneficial, combining the “right” devices, with the “right” architectures, in the “right” way, results in performance (e.g., speed, energy efficiency) gains which far exceed the sum of their individual benefits, while simultaneously providing a rich set of enhanced functionality for applications that otherwise may not be feasible using traditional technologies.”

Max aims to drive nanosystems to both improve computing at the heart of information technology through new approaches (e.g., new system architectures directly enabled by new nanotechnologies). He plans to leverage the richness of new nanomaterials, new computing and memory technologies, and heterogeneous integration to enable new applications beyond the scope of traditional computing. His ultimate goal is to drive nanosystems from concept to reality, resulting in hardware demonstrations of what future electronic systems might look like: from 3D chips with layers of sensing, memory, and logic densely integrated for on-chip ultra-high bandwidth sensing and processing, to computation finely-immersed in biological systems for disease monitoring and nano-implants.